1. Field of the Invention
The present invention relates to a reconfigurable electronic device and, more particularly, to a reconfigurable electronic device having a non-volatile memory function which can be reconstructed by implementing independent lower electrodes including the non-volatile memory function and electrically adjusting a body of a 1D or 2D material or a thin semiconductor thin film.
2. Description of the Prior Art
Si-based sub-8 nm 3D (three-dimensional) devices are expected to be used in 2020s. Due to limitations in structure, material, and characteristics of the Si-based device, new next-generation semiconductor materials and new device s have been increasingly demanded. As countermeasure for overcoming the limitations, 1D semiconductor materials of Si nanowire or carbon nanotube have drawn attention due to characteristics such as quasi-ballistic transport, steep subthreshold swing, and ideal electrostatic coupling. In addition, functions of freely independently adjusting a threshold voltage and a polarity (n-type or p-type) of an FET using the aforementioned 1D material have been known as a core technique in a reconfigurable circuit technique. As an example of the technique, there was a research for a change in polarity (n-type or p-type) of a device using a gate electrode capable of independently applying a voltage to an SWNT device (refer to Non-Patent Document 1) published in 2005.
In addition, as an example of recent researches (refer to Non-Patent Documents 2 to 5), there is a device capable of changing the type from a pMOSFET to an nMOSFET and vice versa by forming Schottky junctions by forming NiS2 at both ends of a lightly-doped Si nanowire, forming a gate insulating film, and after that, adjusting resistance of Schottky junctions using two gate electrodes formed to be isolated from each other in the vicinity of the two Schottky junctions or selectively supplying electrons or holes. It has been reported that a circuit where two unit devices are connected in series based on the change in type of the FET (namely, the same device being changed among the three types of pMOSFET, nMOSFET, and resistor) is implemented to simply change a PMOS inverter into an NMOS inverter or a complementary inverter in operating characteristics. However, the implemented inverter has a shortcoming in time response characteristic in that actual operation speed is several seconds (refer to Non-Patent Document 4). In addition, with respect to a reconfigurable circuit where the number of unit devices is two to four, there is no actual implementation of a circuit where a NOR gate is changed into a NAND gate due to essential problems in a device structure or a manufacturing process.
In the current level of the technique, simulation of operations of logic gates is merely demonstrated (refer to Non-Patent Document 5). Therefore, the reconfigurable circuits published heretofore are good in terms of the studies, but the devices themselves have essential problems as follows. First, in the implementation of the device using the junction between the Si nanowire and the NiS2, there is an essential problem in accurate control of the position of the junction in the manufacturing process. In addition, in the implementation of two top-gates, the two top-gates are not self-aligned with the junction, so that parasitic resistance or capacitance component is greatly increased. Second, in the changing of the type of the device (for example, nMOSFET→pMOSFET), a voltage is always applied to one of the two top-gates, and thus, the number of wire lines and the parasitic component are increased. In order to solve this problem, although a non-volatile memory function can be applied to a gate insulating film, an Eot (equivalent thickness of oxide) is increased, so that current driving performance is greatly deteriorated, and a channel length cannot be miniaturized. Third, even in the case where the device is operated as any type of the MOSFETs, one of the source and the drain necessarily has a Schottky junction, and thus, large low-frequency noise occurring in the Schottky junction essentially limits the applications of the devices. Fourth, in the case where a top-gate-based reconfigurable electronic device or a multi-functional device is implemented according to the technique in the related art, since the area for implementing the unit device becomes large, there is a problem in that a degree of integration is greatly lowered in the implementation of the circuit.
In addition, in the reconfigurable electronic devices according to the technique in the related art, the electrically-formed junction becomes a drain junction and the Schottky junction becomes a source junction, so that off current is small. In the circuit, the positions of the source and the drain are arbitrarily changed, and thus, there is a large shortcoming in terms of off current.
In the specification, the first technique in the related art is a technique disclosed in Non-Patent Documents 2, 4, and 5, the second technique in the related art is a technique disclosed in Non-Patent Document 3, the third technique in the related art is a technique disclosed in Patent Document 2, and the fourth technique in the related art is a technique disclosed in Patent Document 1.    Patent Document 1 mentioned above is U.S. Pat. No. 8,350,602B2, Patent Document 2 is US Patent Application Publication No. US 2013/0313524A1.    In addition, Non-Patent Document 1 is Y. M. Lin, J. Appenzeller, J. Knoch, and P. AVouris, “High-Performance Carbon Nanotube Field-Effect Transistor With Tunable Polarities”, IEEE Trans. Natotech., vol. 4, no. 5, p. 481-488, 2005.    Non-Patent Document 2 is A. Heingzig, S. Slesazeck, F. Kreupl, T. Mikolajick, and W. M. Weber, “Reconfigurable Silicon Nanowire Transistors”, Nano Lett. vol. 12, pp. 119-124, 2012.    Non-Patent Document 3 is M. Mongillo, P. Spathis, G. Katsaros, P. Gentile, and S. D. Franceschi, “Multifunctional Devices and Logic Gates With Undoped Silicon Nanowires, Nano Lett. vol. 12, pp. 3074-3079, 2012.    Non-Patent Document 4 is A. Heingzig, T. Mikolajick, J. Trommer, D. Grimm, and W. M. Weber, “Dually Active Silicon Nanowire Transistors and Circuits with Equal Electron and Hole Transport”, Nano Lett. vol. 13, pp. 4176-4181, 2013.    Non-Patent Document 5 is J. Trommer, A. Heinzig, S. Slesazeck, T. Mikolajick, and W. M. Weber, “Elementary Aspects for Circuit Implementation of Reconfigurable Nanowire Transistors”, IEEE Electron Device Lett. vol. 35, no. 1, pp. 141-143.